Substrate bias through polysilicon line

Details Substrate bias through polysilicon line Substrate bias through polysilicon line

1986-12-23

1989-01-17

James, Andrew J.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 13, 307296R, 307303, H01L 2946, H01L 2966, H01L 2990

Patent

active

047991011

ABSTRACT:
A high-density integrated circuit employing different first and second channel types of insulated gate field effect transistors is disclosed, which comprises at least three stacked wiring layers, the lowest layer being formed of polycrystalline silicon and including silicon gates of the transistors, one of the upper layers being formed of polycrystalline silicon and used for feeding a power supply to some of the transistors and being connected to at least one well region on which the first channel type of transistors are formed, and the other of the upper layers being formed of high-conductivity metal.

REFERENCES:
patent: 3999212 (1976-12-01), Usuda
patent: 4164436 (1979-08-01), Ura et al.
patent: 4282648 (1981-08-01), Yu et al.

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