Semiconductor memory device having a mos transistor and superpos

Details Semiconductor memory device having a mos transistor and superpos Semiconductor memory device having a mos transistor and superpos

1984-05-22

1989-01-17

Carroll, J.

357 51, 357 54, 357 71, H01L 2978, H01L 2702, H01L 2934, H01L 2348

Patent

active

047990937

ABSTRACT:
A semiconductor memory device including a MOS transistor having source and drain electrodes formed on a surface of a semiconductor substrate; an insulating layer formed on a surface of the semiconductor substrate; a first conductive layer which is connected to the source or drain electrodes and is extended on the surface of the insulating layer through the insulating layer; a dielectric layer formed on the surface of said first conductive layer; and a second conductive layer formed on the dielectric layer opposite the first conductive layer, wherein the first conductive layer, the dielectric layer and the second conductive form a capacitor for a memory element.

REFERENCES:
patent: 3617816 (1971-11-01), Riseman et al.
patent: 3699010 (1972-10-01), Nash
patent: 3809625 (1974-05-01), Brown et al.
patent: 3890636 (1975-06-01), Harada et al.
patent: 4012757 (1977-03-01), Koo
patent: 4151607 (1979-04-01), Koyanagi et al.
patent: 4291322 (1981-09-01), Clemens et al.
W. M. Smith, Jr., "Vertical One-Device Memory Cell", IBM Technical Disclosure Bulletin, vol. 15 (1973) pp. 3585-3586.

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