Method for manufacturing dynamic memory cell

Details Method for manufacturing dynamic memory cell Method for manufacturing dynamic memory cell

1987-06-02

1989-01-17

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 47, 437 52, 148DIG18, H01L 2996

Patent

active

047987944

ABSTRACT:
A first semiconductor layer of a P.sup.+ type is formed on a semiconductor substrate of a P.sup.- type and a mask layer is formed on a portion of the first semiconductor layer other than that area where a capacitor is to be formed. A hole is formed in a direction of a thickness of the first semiconductor layer, using the mask layer. An N.sup.+ is formed on the inner surface of the hole with the mask layer as a mask. An insulating film for capacitor formation is formed on the inner surface of the resultant hole and on that atea of the first semiconductor layer where the resultant dynamic memory cell is electrically separated from an adjacent dynamic memory cell. A conductive layer acting as a capacitor electrode is formed on the capacitor formation insulating film. With the conductive layer as a mask, an impurity of an N type is doped into the first semiconductor layer to form a second semiconductor layer of a P.sup.- type in the surface portion of the first semiconductor layer. A MOS transistor is formed in the surface portion of the second conductive layer.

REFERENCES:
patent: 4538166 (1985-08-01), Nakano
patent: 4577395 (1986-03-01), Shibata
patent: 4704368 (1987-11-01), Goth et al.
IBM Technical Disclosure Bulletin, vol. 22, No. 11, Apr. 1980, pp. 4929-4930, Armonk, N.Y., U.S.; T. S. Chang, et al., "Dynamic Random-Access Memory Cell Employing V-Groove Connection to Buried N+ Layer and Optional Capacitor".
Patent Abstracts of Japan, vol. 6, No. 42 (E-98) [920], Mar. 16, 1982; JP-A-56 158 472 (Mitsubishi Denki) 7/81.

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