Semicoductor memory with a timing controlled for receiving data

Details Semicoductor memory with a timing controlled for receiving data Semicoductor memory with a timing controlled for receiving data

1995-10-18

1997-07-08

Yoo, Do Hyun

Static information storage and retrieval

Addressing

Sync/clocking

365194, G11C 700

Patent

active

056469047

ABSTRACT:
In a semiconductor memory, a plurality of semiconductor memory modules are connected through a common clock signal line and one or more other signal lines to an accessing circuit. The accessing circuit has a timing information storage unit for storing predetermined access timing information associated with the respective semiconductor memory modules, and a timing varying unit for varying a data receiving timing at a transfer destination in compliance with a semiconductor memory module to be accessed, on the basis of the access timing information stored in the timing information storage unit.

REFERENCES:
patent: 5414672 (1995-05-01), Ozeki et al.
patent: 5422781 (1995-06-01), DiMarco

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