Method of forming a MOSFET structure with planar surface

Details Method of forming a MOSFET structure with planar surface Method of forming a MOSFET structure with planar surface

1992-05-29

1994-05-10

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437200, 437 69, 437 73, 437231, H01L 21265

Patent

active

053106920

ABSTRACT:
A method is provided for a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A conductive layer is formed over a substrate. A silicon nitride layer is formed over the conductive layer. A photoresist layer is then formed and patterned over the silicon nitride layer. The silicon nitride layer and the conductive layer are etched to form an opening exposing a portion of the substrate. The photoresist layer is then removed. The exposed substrate and a portion of the conductive layer exposed along the sidewalls in the opening are oxidized. An planarizing insulating layer such as spin-on-glass is formed over the silicon nitride layer and in the opening. The insulating layer is etched back to expose the silicon nitride wherein an upper surface of the insulating layer is level with an upper surface of the conductive layer. The silicon nitride layer is then removed. A planar silicide layer is then formed over the conductive layer.

REFERENCES:
patent: 4407696 (1983-10-01), Han et al.
patent: 4566172 (1986-01-01), Bencuya et al.
patent: 4983544 (1991-01-01), Lu et al.
patent: 5086007 (1992-02-01), Ueno
Matsunaga et al., "Selective Polysilicon Oxidation Technology for Defect Free Isolation," 1980 IEDM, pp. 565-568.

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