Electrostatic breakdown protection circuit for a semiconductor i

Details Electrostatic breakdown protection circuit for a semiconductor i Electrostatic breakdown protection circuit for a semiconductor i

1995-08-07

1997-07-08

Gaffin, Jeffrey A.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361111, 257355, H02H 904

Patent

active

056468083

ABSTRACT:
A protection circuit for protecting against electrostatic discharges (ESD) applied to a bonding pad is connected to ground. The ESD is discharged to ground through the protection circuit, which includes a primary transistor for conducting the discharge current to ground and a gate voltage controlling circuit for controlling the gate voltage of the primary transistor. Operation of the protection circuits begins from a low electrostatic voltage, thereby positively enhancing the electrostatic voltage resistance. In particular, when the gate voltage controlling circuit is a secondary transistor, the source terminal of the primary transistor is connected to ground, and the drain terminal is connected to the bonding pad. The source terminal of the secondary transistor is also connected to ground. Its gate terminal and drain terminal are connected to the gate terminal of the primary transistor.

REFERENCES:
patent: 4037140 (1977-07-01), Eaton, Jr.
patent: 4630162 (1986-12-01), Bell et al.
patent: 5144392 (1992-09-01), Brotherton
patent: 5290724 (1994-03-01), Leach
"Dynamic Gate Coupling of NMOS For Efficient Output ESD Protection", Charvaka Duvvury and Carlos Diaz, CH3084-1/92/0000-0141 1992 IEEE/IRPS, pp. 141-150.

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