Video decoder architecture using separate semiconductor substrat

Details Video decoder architecture using separate semiconductor substrat Video decoder architecture using separate semiconductor substrat

1995-06-07

1997-07-08

Chin, Tommy P.

Television

Bandwidth reduction system

Data rate reduction

348416, H04N 732

Patent

active

056466889

ABSTRACT:
A video data processing system (10) has a first substrate (12) and a second substrate (14). A system decoder (16), input buffer (18) and parser (20) are formed on first substrate (12). The parser (20) retrieves video data information from an input data stream and feeds coefficients through a dequantization unit (22) and a transformation unit (24). In addition, motion vector information is output from the parser (20). The second substrate (14) comprises a plurality of picture frame buffers 38, 40 and 44. The frame buffers 38, 40 and 44 are used to store decoded video information. Motion compensation modules 26a and 26b are used to perform predicted calculations on the information received from the video data stream as well as other images that have already been decoded. A raster scan output buffer (46) is used to output the decoded video information.

REFERENCES:
patent: 4367490 (1983-01-01), Riederer
patent: 5159451 (1992-10-01), Faroaudja et al.
patent: 5185819 (1993-02-01), Ng et al.
patent: 5293229 (1994-03-01), Iu
patent: 5317397 (1994-05-01), Odaka et al.

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