Method for tightening VT distribution of 5 volt-only flash EEPRO

Static information storage and retrieval – Floating gate – Particular biasing

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365218, G11C 1134

Patent

active

054814944

ABSTRACT:
There is provided an improved method for tightening the distribution of control gate threshold voltages of erase cells in flash EEPROM devices. A relatively low positive voltage is applied to the source regions of the EEPROM devices during an entire erase cycle. The magnitude of a negative constant voltage applied to control gates of the EEPROM devices is lowered to a predetermined voltage level during the entire erase cycle so as to obtain a tighter threshold voltage distribution. The value of a load resistor coupled between the low positive voltage and source regions is reduced simultaneously to a predetermined value so as to compensate for the increased erase time caused by the lowering of the magnitude of the negative constant voltage. As a result, an improved threshold voltage V.sub.T distribution after erase is obtained without sacrificing any reduction in the erase speed.

REFERENCES:
patent: 5231602 (1993-07-01), Radjy

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