Universal testing circuit and method

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324 73R, G01R 3128

Patent

active

045947112

ABSTRACT:
A test circuit, called a universal testing block (UTB) for on-chip testing of a VLSI subsystem such as a ROM or an ALU has several modes, including test generator and test evaluator, formed on the VLSI chip. The test generator circuit includes means for applying a predetermined test pattern to an input channel of the subsystem and may be a generator for generating pseudorandom test patterns for application to the subsystem. Alternatively, the test generator may be a counter which can be selectively activated to generate a binary up-count. The UTB also has a shift register mode having a serial input and output to enable serial data to be shifted into and out of the subsystem in parallel fashion. The test evaluator circuit receives output signals from the subsystem, and includes a parallel signature analyzer to generate a signature of the subsystem after the application of the test patterns by the input circuit to indicate whether the subsystem is fault-free. Also, means are provided for evaluating the signature and for generating a signal in accordance with the evaluation indicative of whether the subsystem is fault-free.

REFERENCES:
patent: 4320509 (1982-03-01), Davidson
patent: 4498172 (1985-02-01), Bhavsar
patent: 4503536 (1985-03-01), Panzar
patent: 4503537 (1985-03-01), McAnney
Konemann et al., Built-In Test for Complex Digital Integrated Circuits, Fifth European Solid State Circuits Conf., ESSCIRC 79, Sep. 18-21, 1979, Southampton, England, pp. 89-90.
Fasang, Circuit Module Implements Practical Self-Testing, Electronics, vol. 88, No. 1557, May 19, 1982, pp. 164-167.
Hahn et al., VLSI Testing by On-Chip Error Detection, IBM Tech. Disclosure Bulletin, vol. 25, No. 2, Jul. 1982, p. 709.
Carter, Improved Signature Test for VLSI Circuits, IBM Tech. Disclosure Bulletin, vol. 26, No. 3A, Aug. 1983, pp. 965-967.

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