Digital parallel computing circuit for computing p=xy+z in a sho

Details Digital parallel computing circuit for computing p=xy+z in a sho Digital parallel computing circuit for computing p=xy+z in a sho

1983-02-10

1986-06-10

Malzahn, David H.

Boots, shoes, and leggings

364758, G06F 7544

Patent

active

045946787

ABSTRACT:
To increase the computing speed when forming the product of a first binary number (x) and a second binary number (y) and then adding (xy+z) a third binary number (z) by means of a multiplier (mw) and an adder (aw), the individual full-adder stages of the adder (aw) except the stage for the sign digit are inserted as an additional row between the next to the last row and the output row of the multiplier, the full-adder for the sign digit of the output row (az) being also omitted. The two omitted stages are replaced with a sign-correcting stage (vk).

REFERENCES:
patent: 3019977 (1962-02-01), Dvinker et al.
patent: 3761698 (1973-09-01), Stephenson
patent: 3900724 (1975-08-01), McIver et al.
Smith, "External Arithmetic Processor", Computer Design, vol. 17, No. 12, Dec. 1978, pp. 144-149.

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