Process for producing an integrated multi-layer insulator memory

Details Process for producing an integrated multi-layer insulator memory Process for producing an integrated multi-layer insulator memory

1979-07-18

1981-03-24

Ozaki, G.

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

148 15, 148188, 148189, H01L 2122

Patent

active

042578329

ABSTRACT:
An integrated multi-layer insulator memory cell is produced via silicon-gate technology, with self-adjusting, overlapping polysilicon contact wherein a gate oxide of a peripheral transistor is produced after the application of multi-layer insulating layer comprised of a storage layer and a "blocking" layer. The "blocking" layer consists of an oxynitride layer formed by oxidation of a silicon nitride layer surface or an additionally applied SiO.sub.2 layer and has a layer thickness of about 5 to 30 nm. Such "blocking" layer prevents an undesired injection of charge carriers from the silicon-gate electrode. It also provides means for forming a self-adjusting, overlapping polysilicon contact.

REFERENCES:
patent: 3873372 (1975-03-01), Johnson
patent: 4001048 (1977-01-01), Meiling et al.
patent: 4102733 (1978-07-01), De La Moneda et al.
patent: 4140548 (1979-02-01), Zimmer
patent: 4149307 (1979-04-01), Henderson
Chen, IEEE Transactions on Electron Devices, vol. ED-24, May 1977, pp. 584-586.

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