Patent
1989-01-06
1991-02-12
Mintel, William
357 40, 357 41, 357 45, H01L 2702
Patent
active
049928457
ABSTRACT:
An internal logic gate portion (3) is provided in the central portion of a semiconductor chip (1), input/output buffers (4) are provided to surround the internal logic gate portion (3), and bonding pads (2) are provided in the peripheral portions of the semiconductor chip (1) corresponding to input/output buffer cells (5) in the input/output buffer. Each of the input/output buffer cells (5) comprises an output P-MOS portion (6), an output N-MOS portion (7), an input/logic P-MOS portion (8) and an input/logic N-MOS portion (9), which are respectively arranged in a single line in the direction from the bonding pads (2) to the internal logic gate portion (3). In the above described structure, the size of each of the input/output buffer cells (5) in the pad arranging direction of the bonding pads (2) is decreased, so that the number of input/output pins can be increased according to the decreased use of space in the pad arranging direction required by each input/output buffer cell (5).
REFERENCES:
patent: 4591894 (1986-05-01), Kawakami
patent: 4651190 (1987-03-01), Suzuki et al.
patent: 4766475 (1988-08-01), Kawashima
patent: 4771327 (1988-09-01), Usui
Blumberg et al, "A 640K Transistor Sea-of-Gates 1.2.mu. Micron HCMOS Technology," 1988 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, Feb. 17, 1988, pp. 74-75 & 308.
Arakawa Takahiko
Hanibuchi Toshiaki
Kishida Satoru
Okuno Yoshihiro
Sakashita Kazuhiro
Mintel William
Mitsubishi Denki & Kabushiki Kaisha
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