Testing embedded arrays

Details Testing embedded arrays Testing embedded arrays

1974-12-20

1976-06-01

Rolinec, R. V.

Electricity: measuring and testing

Plural, automatically sequential tests

235153AC, 235153AK, G01R 1512

Patent

active

039612546

ABSTRACT:
An LSI semiconductor device includes a memory array incorporating address, data and buffer registers, and associated combinatorial and/or sequential logic circuitry. The array is "embedded" in the sense that the memory array is not directly accessible, either in whole or in part, from the input and output terminals or pads of the device. To facilitate testing, means which bypass the associated logic circuitry are provided for scanning information directly into the address and data registers. The information so introduced is shifted through the register strings. The interconnections from the associated logic circuitry are inhibited during the testing mode while the information shifting means are inhibited during an operative mode. The information scanned into the registers may be scanned out to determine whether there is a defect or problem in the register strings. Output levels from the array are compared with an expected output.

REFERENCES:
patent: 3387276 (1968-06-01), Reichow
patent: 3758761 (1973-09-01), Henrion

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