Program cache apparatus which associates the physical address of

Details Program cache apparatus which associates the physical address of Program cache apparatus which associates the physical address of

1994-08-22

1997-04-08

Lane, Jack A.

395403, G06F 942

Patent

active

056196962

ABSTRACT:
When a central processing unit requests a program, the central processing unit loads a program from an external storage device onto a physical page. The physical address of the physical page where this program is stored is associated with a logical address in a program cache space. Information about addresses in this program is translated in this program cache space. Then, the physical address of the physical page where the program is loaded is associated with a logical address in a process space. Therefore, the central processing unit can thereafter access the program in the process space without copying a physical page for address alteration. When the central processing unit executes writing on the program in the process space later, the physical page is copied.

REFERENCES:
patent: 5175842 (1992-12-01), Totani
patent: 5475840 (1995-12-01), Nelson et al.
Goodman, J.R. "Coherency for Multiprocessor Virtual Address Caches." Proceedings of the Second International Conference on Architectural Support for Programming Languages and Operating Systems. IEEE. 1987. Oct. 1987.

Affiliated with

Also associated with

Rating

Program cache apparatus which associates the physical address of does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Program cache apparatus which associates the physical address of, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Program cache apparatus which associates the physical address of will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2403026