Queue system having a time-out feature and method therefor

Details Queue system having a time-out feature and method therefor Queue system having a time-out feature and method therefor

1994-02-22

1997-04-08

Heckler, Thomas M.

395287, 395427, G06F 1300

Patent

active

056196873

ABSTRACT:
A queue memory system (10) provides a flexible memory transfer system which uses a single transaction to either store a memory value in a queue or to retrieve the memory value from the queue. A queue controller (20) controls the transfer of data between a queue memory (18) and the peripheral devices (22, 24). The queue controller generally includes a register (52, 62) which indicates an address to be accessed and a direction control signal. Additionally, each peripheral device has a queue control register which is configured to access a selected channel of the queue memory. The queue memory system described herein also efficiently uses the cycle time of a central processing unit (12) of the system to perform queue accesses without disrupting more general processing steps. For example, the queue memory system will wait (for up to thirty-two timing cycles) for a timing cycle in which the central processing unit does not require use of a bus. At that time, the queue memory system will transfer data between the queue and a peripheral device. An alternate option is to force the central processing unit to freeze operation so that data will be transferred immediately.

REFERENCES:
patent: 3804987 (1974-04-01), Cooper
patent: 4665483 (1987-05-01), Ciacci et al.
patent: 5193193 (1993-03-01), Iyer
patent: 5283902 (1994-02-01), Dorn

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