Boots – shoes – and leggings
Patent
1996-05-31
1998-12-01
Sheikh, Ayaz R.
Boots, shoes, and leggings
395739, 395725, 395325, 364513, G06F 1336
Patent
active
058451315
ABSTRACT:
A multiprocessor system has a shared bus and a plurality of processor modules, wherein the shared bus includes an interrupt bus and each of the processor module contains an interrupt controller. The interrupt controller for performing an interrupt bus arbitration includes an interrupt bus arbiter. The interrupt bus arbiter has N number, e.g., 8 of arbitration cells, wherein each cell simultaneously receives a corresponding bit of the arbitration information, lower bits of the corresponding bit and corresponding lower bits of the wired-ORed interrupt bus data to generate an interrupt bus gain signal when the corresponding bits represent one logic state and the lower bits represent the other logic state; and a decision circuit connected to the arbitration cells for generating an interrupt bus gain decision signal when the interrupt bus gain signal is received.
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patent: 5265215 (1993-11-01), Fukuda et al.
patent: 5410710 (1995-04-01), Sarangdhar et al.
patent: 5495615 (1996-02-01), Nizar et al.
Daewoo Telecom Ltd.
Sheikh Ayaz R.
Thlang Eric S.
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