Patent
1997-03-03
1998-12-01
Ellis, Richard L.
395386, G06F 930
Patent
active
058451021
ABSTRACT:
A superscalar microprocessor implements a microcode instruction unit with an MROM entry point generator. The MROM entry point generator generates the first address of a microcode sequence that effectuates the function of an MROM instruction. The address of the microcode instruction depends upon the prefix bytes, the opcode bytes and the ModR/M byte of the MROM instruction. To expedite the generation of the first address, or entry point address, a plurality of entry point address generators generate entry point addresses based on a presumed state of the prefix byte. In parallel with the generation of the entry point addresses, a prefix decoder decodes the prefix byte to determine the state of the prefix byte. The output of the entry point address generator that generated an entry point address based on the actual prefix byte is selected. By decoding the prefix byte in parallel with entry point address generation, the propagation delay associated generation of entry point addresses is advantageously reduced.
REFERENCES:
patent: 5537629 (1996-07-01), Brown et al.
patent: 5630083 (1997-05-01), Carbine et al.
patent: 5689672 (1997-11-01), Witt et al.
Pentium Processor User's Manual, vol. 3: Architecture and Programming Manual, Intel Corporation, 1993, pp. 25-1 -25-5.
Mahalingaiah Rupaka
Miller Paul K.
Advanced Micro Devices , Inc.
Ellis Richard L.
Kivlin B. Noel
Winder Patrice L.
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