Monolithic integrated circuit structure and method of fabricatio

Metal working – Method of mechanical manufacture – Assembling or joining

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29571, 29578, 29576W, 357 42, 357 50, 148DIG70, 148DIG85, 148DIG86, H01L 2176, H01L 2182

Patent

active

045934592

ABSTRACT:
Method of forming a substrate for fabricating CMOS FET's by forming sections of N and P-type conductivity in a body of silicon. Grooves are etched in the N and P-type sections to produce N and P-type sectors encircled by grooves. The surfaces of the grooves are oxidized, the grooves are filled with polycrystalline silicon, and exposed surfaces of the polycrystalline silicon are oxidized to form barriers which encircle the sectors and electrically isolate them. Shallow trenches are etched in regions of the body outside the N and P-type sectors and the trenches are filled with regions of silicon dioxide. A pair of complementary FET's are fabricated in the two sectors and a metal interconnection between them overlies a portion of a region of silicon dioxide.

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