In-place present state/next state registers

Details In-place present state/next state registers In-place present state/next state registers

1994-12-29

1997-04-08

Envall, Jr., Roy N.

Excavating

371 404, 375341, G06F 1110, H03M 1312

Patent

active

056195141

ABSTRACT:
A technique for efficiently utilizing memory in determining a next state accumulated cost in a communications system or a Viterbi decoder. The system includes a memory having an array of registers. A first present state accumulated cost is retrieved from a first storage register of the array. A second present state accumulated cost is retrieved from a second storage register of the array. A first next state accumulated cost is calculated based on the first present state accumulated cost. The first next state accumulated cost is stored in the first storage register of the array. An advantage of the invention is that such a technique requires less memory to calculate and store accumulated costs. The number of memory locations required is one for each individual state, which is substantially half of the memory locations required previously.

REFERENCES:
patent: 4493082 (1985-01-01), Cumberton et al.
patent: 4583078 (1986-04-01), Shenoy et al.
patent: 4748626 (1988-05-01), Wong
patent: 4868830 (1989-09-01), Pollara-Bozzola
patent: 5272706 (1993-12-01), Park
patent: 5465275 (1995-11-01), Blaker et al.

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