Semiconductor memory device with a plurality of bonding pads arr

Details Semiconductor memory device with a plurality of bonding pads arr Semiconductor memory device with a plurality of bonding pads arr

1995-09-28

1997-04-08

Nelms, David C.

Static information storage and retrieval

Addressing

Plural blocks or banks

365 51, 365226, G11C 800, G11C 502

Patent

active

056194722

ABSTRACT:
A semiconductor memory comprising core blocks 1, 2, 3 and 4 each comprising memory cell arrays each having a plurality of memory cells in a matrix and sense amplifiers and decoders accompanying the memory cell arrays. An inter-block region is arranged among the core blocks wherein data signal lines, address signal lines and control signal lines are provided. Pad arrays IO Pad and A Pad each comprising a plurality of pads and buses IO Bus and A Bus are arranged among the core blocks. The buses A Bus are jogged in a connection region. The buses IO Bus and A Bus are arranged successively in the inter-block region and the data signal lines, the address signal lines and the control signal lines are connected to the buses A Bus and IO Bus in the inter-block region.

REFERENCES:
patent: 5355369 (1994-10-01), Greenberger et al.
patent: 5467300 (1995-11-01), Komarek et al.

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