Semiconductor device and method of manufacturing the same

Details Semiconductor device and method of manufacturing the same Semiconductor device and method of manufacturing the same

1984-12-26

1987-05-05

Edlow, Martin H.

357 55, 357 234, 357 2312, 357 41, H01L 2978, H01L 2906, H01L 2702

Patent

active

046636447

ABSTRACT:
Disclosed are various semiconductor devices having vertical-type MISFETs wherein the source and drain regions of the MISFETs are spaced from each other in a direction perpendicular to the main surface of the semiconductor substrate containing such MISFETs. In a specific embodiment, a plurality of such MISFETs can be arrayed in a substrate, to form a memory device, with a common gate electrode, buried in the substrate, being used for a plurality of the memory cells, such buried gate electrode constituting the word line for the memory cells, with the data line extending over the surface of the substrate. This structure provides for increased miniaturization, without decrease in channel width of the MISFET, and provides for a flatter device surface due to the buried combination gate electrode/word lines.

REFERENCES:
patent: 4198693 (1980-04-01), Kuo
patent: 4219836 (1980-08-01), McElroy
patent: 4462040 (1984-06-01), Ho et al.
patent: 4541001 (1985-09-01), Schutten et al.
Rodgers et al., "VMOS Memory Technology", IEEE Journal of Solid-State Circuits, vol. SC-12, No. 5, Oct. 1977, pp. 515-523.

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