Static information storage and retrieval – Floating gate – Particular biasing
Patent
1996-12-06
1998-12-01
Nelms, David
Static information storage and retrieval
Floating gate
Particular biasing
36518524, 3651853, 36518533, 365218, G11C 1134
Patent
active
058448470
ABSTRACT:
In a nonvolatile floating gate memory cell array, memory cells can become over-erased wherein their threshold voltage becomes near zero volts or even slightly negative. To correct over-erased cells and raise their threshold voltages to a normal level, a nonvolatile memory includes a control circuit for applying a programming voltage (approximately 5V) to the bit lines of the memory cell array and a lower voltage (approximately 2V) to the word lines of the memory cell array. The lower voltage is selected to be less than the threshold voltage (e.g., 3V) for a normal cell such that normal cells are not affected. However, the cells in an over-erased state will become active by the lower threshold voltage and begin conducting. A channel current flows to the over-erased memory cells and channel hot electrons induced by this channel flow into the floating gate of the memory cell raises the threshold voltage (VTM) of the memory cell to a normal level.
REFERENCES:
patent: 5237535 (1993-08-01), Mielke et al.
patent: 5377147 (1994-12-01), Merchant et al.
patent: 5537665 (1996-07-01), Patel et al.
patent: 5594689 (1997-01-01), Kato
Japanese Office Action, Dated Apr. 7, 1998: Translation Attached.
NEC Corporation
Nelms David
Phan Trong
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