Circuit arrangement for processing picture data

Details Circuit arrangement for processing picture data Circuit arrangement for processing picture data

1986-07-01

1988-09-27

Groody, James J.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358183, 358 22, 358185, H04N 514, H04N 5222

Patent

active

047745789

ABSTRACT:
Several picture memories (SP1, SP2, SP3, SP4) are provided, in each of which the picture data of a picture are stored. The input of a logic circuit (VL) is connected to the outputs of the picture memories. The output signals of the logic circuit are fed to the picture memories. The logic circuit (VL) may comprise a multiplexer, to the control inputs (A, B, C) of which the signals to be interlinked are fed, and to the data inputs (E1, E2 . . . E8) of which the code signals are fed characterizing the kind of logical interconnection. The main field of application is in the digital evaluation of television pictures.

REFERENCES:
patent: 3976982 (1976-08-01), Eiselen
patent: 4689823 (1987-08-01), Wojcik et al.
Der Elektroniker, No. 1 (1985), pp. 59-67.

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