Personalizable gate array devices

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics

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257202, 257204, 257209, H01L 2702, H01L 2710, H01L 2715

Patent

active

056190620

ABSTRACT:
Customizable semiconductor devices, integrated circuit gate arrays and techniques to produce same are disclosed. The devices comprise integrated circuit blanks having a collection of semiconductor elements and at least one metal layer including fusible links interconnecting said collection of semiconductor elements into an inoperably connected integrated circuit blank. At least one metal layer is first etched thereby to define a pattern of conductors. A passivation layer is provided over at least one metal layer, afterwhich at least one metal layer is etched a second time for selectably removing the fusible links, thereby converting the inoperable integrated circuit blank into a selected operable electronic function.

REFERENCES:
patent: 3925684 (1975-12-01), Gaskill
patent: 4045310 (1977-08-01), Jones et al.
patent: 4124899 (1978-11-01), Birkner
patent: 4197555 (1980-04-01), Uehara
patent: 4233671 (1980-11-01), Gerzberg
patent: 4238839 (1980-12-01), Redfern
patent: 4240094 (1980-12-01), Mader
patent: 4295149 (1981-10-01), Balyoz
patent: 4325169 (1982-04-01), Ponder
patent: 4356504 (1982-10-01), Tozun
patent: 4412237 (1983-10-01), Matsumura
patent: 4455495 (1984-06-01), Masuhara
patent: 4476478 (1984-10-01), Noguchi
patent: 4536949 (1985-08-01), Takayama
patent: 4590589 (1986-05-01), Gerzberg
patent: 4651190 (1987-03-01), Suzuki
patent: 4674452 (1987-06-01), Zommer
patent: 4700214 (1987-10-01), Johnson
patent: 4758745 (1988-07-01), Elgamal
patent: 4795720 (1989-01-01), Kawanabe
patent: 4924287 (1990-05-01), Orbach
N.H.E. Weste et al. "Principles of CMOS VLSI Design, A System Perspective", Addison-Wesley (Jun. 1988) pp. 241-4, 370, 374.
North, J. et al. "Laser Coding . . . " IEEE Int'l. of Solid State Devices, vol. SC-II, No. 4.
Aug. 1976, pp. 500-505.
Schuster, S. "Selective Metallization . . . " IBM Tech Disc. Bull. vol. 15, No. 2, Jul. 1972, p. 551.
Raffel, J.I. et al. "A Wafer Scale . . . " IEEE, Journal of Solid State Circuits, vol. SC-20., No. 1., Feb. 1985.
Disclosed Figures BAS-1, BAZ, and BA-3 of US Pat. 5049969.
C.J. Boisvert, "One Day Prototype Laser . . . ", 8079 Electro 186 .alpha. Mini/Micro Northeast, 11 (1986) Conference Record, Los Angeles CA U.S. p.
R.M. Fisher, "Nonvolatile Memories" IEEE International Solid State Circuits Conference, vol. 25, Feb. 1982, NY. USA pp. 114-115.
Ono, K "A Method for Producing a Semiconductor Integrated Circuit", Kokai JP 53-78789 Japan (English Translation).

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