Consolidated chip design for wire bond and flip-chip package tec

Details Consolidated chip design for wire bond and flip-chip package tec Consolidated chip design for wire bond and flip-chip package tec

1996-07-26

1998-12-01

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

257780, 257781, H01L 2348, H01L 2352, H01L 2940

Patent

active

058443177

ABSTRACT:
A semiconductor structure and method of fabrication are provided in which permanent external electrical connection to active circuitry in the structure can be made through either a wire bond pad or metal bump formed thereon. A final metallization including a wire bond pad is disposed over and electrically connected with the active circuitry. An insulating material film is disposed over the final metallization leaving the wire bond pad and a portion of the final metallization laterally displaced from the pad exposed. A metal bump contacts the laterally displaced exposed portion of the final metallization. The wire bond pad is electrically coupled with and laterally displaced from the metal bump through the final metallization. The metal bump and wire bond pad are configured to facilitate electrical connection of the semiconductor structure with an external connector, such as a modular packaging substrate. The structure may also be used for testing and burning in a semiconductor die without direct physical contact of the external testing device to the wire bond pad.

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Bona et al., "Optical Networks for VLSI-Interconnects on Flexible GaAs Substrate", IBM Technical Bulletin, vol. 35, No. 2, pp. 26-27, Jul. 1992.

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