Memory device with a test mode

Details Memory device with a test mode Memory device with a test mode

1990-09-26

1993-01-05

Atkinson, Charles E.

Excavating

371 151, 365201, G01R 3128

Patent

active

051777452

ABSTRACT:
A memory device is described. The memory device includes a memory array. An address buffer is provided for storing a plurality of bits of an address for addressing the memory array. The address is applied as an input of the address buffer. Each bit of the address can be in a first voltage state, a second voltage state, and a third voltage state. When at least one bit of the plurality of bits of the address is in the third voltage state, a test mode for the memory device is initiated. Circuitry is also provided for allowing the entire memory array to be addressed. The circuitry detects the state of two bits of the address and converts two corresponding address bits stored in the address buffer to the first voltage state if the two bits of the address are in the third voltage state. The circuitry is coupled to the address buffer. A method of triggering a memory device is also described.

REFERENCES:
patent: 4811299 (1989-03-01), Miyazawa et al.
patent: 4951254 (1990-08-01), Ontrop et al.
patent: 5051995 (1991-09-01), Tobita
patent: 5072137 (1991-12-01), Slemmer
patent: 5077738 (1991-12-01), Larsen et al.
Intel Corporation 1989 Memory Components Handbook, pp. 4-77 to 4-87 (Oct. 1988).

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