Demultiplexer for a serial and isochronous multiplex signal

Details Demultiplexer for a serial and isochronous multiplex signal Demultiplexer for a serial and isochronous multiplex signal

1991-09-09

1993-01-05

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

371 371, 371 401, H04J 304

Patent

active

051777428

ABSTRACT:
The described demultiplexer is intended for a serial and isochronous multiplex signal consisting of Q isochronous tributary signals interleaved bock-by-block, each block containing K bits. An associated multiplexer is also described. In order to keep the required memory capacity in a demultiplexer as small as possible, a write/read memory (5) is utilized, into which the bits of the multiplex signal are cyclically written and from which, simultaneously, the bits of the tributary signals are read out cyclically. A write/read control (4) coordinates the writing and reading processes in a manner such that no collisions occur. In an exemplary embodiment the bits of the multiplex signal are written into the write/read memory (5) bit-by-bit by means of a serial-to-parallel converter (2). Reading is effected bit-by-bit while utilizing read logics (81, 82, 83, 84) which are also controlled by the write/read control (4) via addresses. At the output (91, 92, 93, 94) of each of these read logics (81, 82, 83, 84) the tributary signals are available in a serial form.

REFERENCES:
patent: 4485470 (1984-11-01), Reali
patent: 4727541 (1988-02-01), Mori et al.
patent: 4731783 (1988-03-01), Fontanes
patent: 4750172 (1988-06-01), Hornung et al.
patent: 4805165 (1989-02-01), Kawamura et al.
patent: 4914655 (1990-04-01), Johannes et al.

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