Boots – shoes – and leggings
Patent
1991-11-22
1993-01-05
Mai, Tan V.
Boots, shoes, and leggings
G06F 752
Patent
active
051777037
ABSTRACT:
A division circuit having a plurality of stages based on a repeat arithmetic operation method, with each stage having: a constant multiplier for multiplying a divisor by a predetermined constant multiple; a carry save type adder (CSA) for performing an addition operation between a dividend and the constant multiple value of the divisor provided from the constant multiplier, then for outputting a sum component and a carry component as a result of the addition operation; shifters for shifting the sum component and the carry component by a shift amount in accordance with a radix, respectively; a carry propagation adder (CPA) for performing an addition operation between the upper bits of the shifted sum component and the shifted carry component obtained by the shifter by predetermined bits; and comparators for outputting a part of a quotient having a plurality of bits by comparing the result obtained by the CPA and the constant multiple value of the divisor, then for determining the value of the constant multiple of the constant multiplier based on the comparison result. In the division circuit, the value of the constant multiple at the following constant multiplier is determined by the output of the comparator and the output of the CPA, the sum component and the carry component obtained by the CSA are provided to a CSA in the following stage, and the dividend and zero in place of the sum component and the carry component are input to the CSA in the first stage.
REFERENCES:
patent: 4546447 (1985-10-01), Sawada
patent: 4722069 (1988-01-01), Ikeda
patent: 4754422 (1988-06-01), Sakai et al.
patent: 4797849 (1989-01-01), Nakano
patent: 5105378 (1992-04-01), Mori
Computer No Kousokuenzanhoushiki, by Wang, for Computer Arithmetic Chapter 7, Sec 9, pp. 236-240, 1980.
Kabushiki Kaisha Toshiba
Mai Tan V.
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