Fishing – trapping – and vermin destroying
Patent
1991-10-22
1993-01-05
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 67, 148DIG50, H01L 2176
Patent
active
051770288
ABSTRACT:
A method of forming isolation trenches and mesa areas in a semiconductor substrate and of forming FETs in the mesa areas is disclosed. The method includes providing a first oxide layer, a first undoped polysilicon layer, and an etch stop layer on a silicon substrate. Isolation trenches and mesa areas are then defined by etching the substrate. A second oxide layer is provided to fill the isolation trenches, and is subsequently etched to remove second layer oxide above the mesa areas, thus exposing the first polysilicon layer. The method further comprises providing a second, conductively doped polysilicon layer over the exposed first polysilicon layer, wherein the first polysilicon layer is autodoped by the second polysilicon layer in a subsequent step. The first and second layers of polysilicon are patterned and etched to define FET gates in the mesa areas, with the first oxide layer beneath the first polysilicon layer being utilized as gate oxide.
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patent: 4892614 (1990-01-01), Chapman et al.
patent: 4927777 (1990-05-01), Hsu et al.
patent: 5106772 (1992-04-01), Lai
Chaudhari C.
Hearn Brian E.
Micro)n Technology, Inc.
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