Scannable register with delay test capability

Electrical pulse counters – pulse dividers – or shift registers: c – Shift register – Particular input circuit

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365 73, 365 78, 365154, 36523008, 364716, G11C 506, G06F 1300

Patent

active

050688812

ABSTRACT:
A scan-register having first and second data input ports (SYS.sub.-- DATA, SCAN.sub.-- IN), a data output port, and inputs for at least first, second, third, and fourth control signals (SYS.sub.-- CLK, M.sub.-- LOAD, CLK.sub.-- B, CLK.sub.-- A).
The scan-register comprises the following elements: first means (12A) having inputs coupled to the first and second data input ports for selectively storing data appearing on one of the said data input ports in accordance with the occurrence of a predefined combination of states of at least the first and second control signals; second menas (10A) having at least one input coupled to the second data input port for selectively storing data appearing on the second data input port in accordance with the occurrence of a predefined state of at least the third control signal; and third means (12B) having at least one input port coupled to an output of one of the first and second means, and further having an output coupled to the data output port, for selectively storing data stored in either the first or second means in accordance with the occurrence of a predefined state of at least the fourth control signal and providing the data stored therein to the data output port.

REFERENCES:
patent: 4293919 (1981-10-01), Dasgupta et al.
patent: 4495629 (1985-01-01), Zasio et al.
patent: 4782283 (1988-11-01), Zasio
patent: 4922457 (1990-05-01), Mizukami
"A Logic Design Structure for LSI Testability", E. B. Eichelberger and T. W. Williams, Proceedings of the 14th Annual Design Automotion Conference, Jun., 1977, pp. 462-468.
"Testing for Timing Faults in Synchronous Sequential Integrated Circuits", Yashwant K. Malaiya and Ramesh Narayanaswamy, pp. 560-571, Proceedings of the 1983 International Test Conference (IEEE).

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