Multiprocessor system having shared memory divided into a plural

Details Multiprocessor system having shared memory divided into a plural Multiprocessor system having shared memory divided into a plural

1991-10-29

1994-12-20

Dixon, Joseph L.

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3642281, 3642292, 3642301, 3642386, 364240, 3642423, 3642443, 3642545, 3642551, 3649414, 3649422, 3649423, 364955, 3649576, G06F 1336, G06F 940

Patent

active

053752155

ABSTRACT:
A multiprocessor system of the present invention has an address bus, a data bus, first and second processors, four access queues, and a shared memory divided into four banks. The four access queues are constituted by first-in first-out memories for buffering a plurality of access-request addresses transmitted through the address bus. Even if continuous access requests are addressed to one bank of the shared memory, a succeeding access request need not wait for a previous access request to be finished. Accordingly, the throughput of the system can be improved greatly.

REFERENCES:
patent: 4992930 (1991-02-01), Gilfeather et al.
patent: 5023776 (1991-06-01), Gregor
patent: 5317726 (1994-05-01), Horst

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