Patent
1994-02-07
1994-12-20
Harvey, Jack B.
G06F 1210
Patent
active
053752147
ABSTRACT:
A dynamic address translation mechanism uses a single translation look aside buffer (TLB) facility for pages of various sizes. The single TLB is supported by a small amount of special hardware. This hardware includes logic for detecting a page size prior to translation and generating a mask. The logic selects a set of virtual address bits for addressing the entries in the TLB. Parts of the virtual address are masked and merged with the address read out of the TLB to form the real address.
REFERENCES:
patent: 3675215 (1972-07-01), Arnold et al.
patent: 4096573 (1978-06-01), Heller et al.
patent: 4355355 (1982-10-01), Butwell et al.
patent: 4356549 (1982-10-01), Chueh
patent: 4373179 (1983-02-01), Katsumata
patent: 4766537 (1988-08-01), Zolnowsky
patent: 4797814 (1989-01-01), Brenza
patent: 4835734 (1989-05-01), Kodaira et al.
patent: 4903234 (1990-02-01), Sakurasa et al.
patent: 4992936 (1991-02-01), Katada et al.
patent: 5058003 (1991-10-01), White
patent: 5133058 (1992-07-01), Jensen
patent: 5263140 (1993-11-01), Riordan
Holden et al., "Intergrated Memory Management for the MC68030" IEEE International Conference on Computer Design, 1987 pp. 586-589.
Mirza Jamshed H.
White Steven W.
Harvey Jack B.
International Business Machines - Corporation
Lane Jack A.
LandOfFree
Single translation mechanism for virtual storage dynamic address does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Single translation mechanism for virtual storage dynamic address, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Single translation mechanism for virtual storage dynamic address will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2390340