Facsimile and static presentation processing – Facsimile – Specific signal processing circuitry
Patent
1990-04-30
1991-11-26
Groody, James J.
Facsimile and static presentation processing
Facsimile
Specific signal processing circuitry
358140, 358148, 382 47, H04N 3223, H04N 701, H04N 504
Patent
active
050687310
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
This invention relates generally to a video processing circuit which enlarges or reduces video image in the vertical direction and, in particular, to a vertical address control at the time of writing into or reading from a video memory.
FIG. 4 is a block diagram of a video processing circuit of the prior art which enlarges or reduces video image. In the figure, 31 is a signal divider for dividing horizontal sync signal, HS, 32 is a vertical address counter, and 33 is a video memory.
Video memory 33 specifies a horizontal sync signal, HS, which forms one visual image by vertical address, and specifies each dot which is converted from analog to digital at a certain specified number of dots for each horizontal sync signal, for example 960 dots, by horizontal address.
In the case of displaying enlarged or reduced video image responding to the luminance signal stored in video memory 33, signal divider 31 divides horizontal sync signal, HS, into 1/2.sup.N and supplies the divided signal to vertical address counter 32, which controls vertical address of video memory 33, as a count up signal. Vertical address counter 32 is counted by a divided signal, and the counted value becomes the address for the vertical direction.
There is a problem, however, with the video processing circuit of the prior art in that arbitrary enlargement or reduction is absolutely impossible because in the case of writing a luminance signal into a vertical address of video memory 33 which is specified by vertical address counter 32, the reduction is only by 1/2.sup.N and in the case of reading a luminance signal from video memory 33, the reduction is also only by 1/2.sup.N.
This invention solves the foregoing problem with an objective to provide a video processing circuit which is capable of arbitrary and easy enlargement and reduction of the video signal and the resultant video image.
SUMMARY OF THE INVENTION
The video processing circuit in connection with this invention comprises a phase lock loop circuit (referred to hereinafter as PLL circuit) wherein a vertical sync signal of video signal is applied to one of the phase comparative inputs of the circuit, and a signal divider, which receives a VCO signal from the PLL circuit, divides it into 1/N (N is an integer), and supplies this divided signal to the other phase comparative input of the circuit. Then, the VCO signal from the PLL circuit is counted by a vertical address counter, and at the time of access to the video memory this value is employed as a vertical address.
Also, a vertical address memory is placed between a vertical address counter and a video memory. This vertical address memory synchronously stores the counted value of the vertical address counter in the input of horizontal sync signal and supplies the stored value to the video memory as a vertical address.
Also, another memory which stores the dividing ratio, N, is placed in a signal divider, and it is constructed so that inside the memory can be addressed by separately connected CPU, personal computer, or the like.
Thus, according to this invention, since the clock frequency of a video memory can be adjusted by employing a PLL circuit, very stable properties are inexpensively obtained. Also, since it is not affected by the frequency of multiple video signals, it can respond to various types of multiple video signals.
Further, enlargement and reduction of video image can be easily ascertained or adjusted by separately connected CPU, personal computer, or the like, making it extremely beneficial in the future field of digital video.
Still further, since a video memory can be easily put into practical use, such as a video digitizer for writing in and a video display panel and the like for read from, this invention is indispensable for a video processing circuit, such as video personal computers, intelligent peripherals, and the like which will become increasingly popular in use in the future.
Other objects and attainments together with a fuller understanding of the invention will become app
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Burgess Glenton B.
Carothers, Jr. W. Douglas
Groody James J.
Main Richard B.
Seiko Epson Corporation
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