Laminated substrate for semiconductor device and manufacturing m

Details Laminated substrate for semiconductor device and manufacturing m Laminated substrate for semiconductor device and manufacturing m

1994-04-28

1994-12-20

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437974, 437 64, 437 67, 148DIG12, H01L 2176

Patent

active

053745825

ABSTRACT:
A method for fabricating a laminated substrate for a semiconductor device having a high voltage power device and a low voltage element formed in a region isolated from the power device with a P-N junction. The region for the low voltage element is formed on a buried layer of P type formed in the region of N type in which the power device is formed and surrounded by a isolating region of P type reaching the buried layer from the surface of the laminated substrate.

REFERENCES:
patent: 4532003 (1985-07-01), Beasom
patent: 4638552 (1987-01-01), Shimbo et al.
patent: 4963505 (1990-10-01), Fujii et al.
patent: 5097314 (1992-03-01), Nakagawa et al.
patent: 5100814 (1992-03-01), Yamaguchi et al.
patent: 5234535 (1993-08-01), Beyer et al.

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