Method of fabricating stacked capacitor cell memory devices

Details Method of fabricating stacked capacitor cell memory devices Method of fabricating stacked capacitor cell memory devices

1993-06-03

1994-12-20

Fourson, George

Fishing, trapping, and vermin destroying

437 52, 437919, H01L 21265, H01L 2170, H01L 2700

Patent

active

053745760

ABSTRACT:
A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.

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