Method of forming a self-aligned thin film transistor

Details Method of forming a self-aligned thin film transistor Method of forming a self-aligned thin film transistor

1994-02-23

1994-12-20

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437101, 437909, 437 52, H01L 21265

Patent

active

053745736

ABSTRACT:
A thin film transistor with self-aligned source and drain regions is fabricated, in one embodiment, by forming an opening (124) in a dielectric layer (118) which overlies a substrate (116). A semiconductive sidewall spacer (130) is formed around the perimeter (126) of the opening (124) and adjacent to the sidewall (128) of the opening (124). A first electrode region (120) is electrically coupled to a first portion of the semiconductive sidewall spacer (130) at a first location along the perimeter (126) of the opening (124) which lies only in the second lateral half of the opening (124). A second electrode region (122) is electrically coupled to a second portion of the semiconductive sidewall spacer (130) at a second location along the perimeter (126) of the opening (124) which lies only in the first lateral half of the opening (124). A dielectric layer (132) is formed adjacent to the semiconductive sidewall spacer (130). A control electrode (134) is formed adjacent to the dielectric layer (132).

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"Impact of Surrounding Gate Transistor (SGT) for Ultra-High-density LSI's," by H. Takato et al., IEEE Transactions on Electron Devices, vol. 38, No. 3, Mar. 1991, pp. 573-577.

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