Method for producing a planar surface in integrated circuit manu

Details Method for producing a planar surface in integrated circuit manu Method for producing a planar surface in integrated circuit manu

1990-04-30

1991-11-26

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437944, 437235, 148DIG100, H01L 21469

Patent

active

050682075

ABSTRACT:
A planar surface is produced in integrated circuit processing by patterning a bilevel structure of a conductor and a sacrificial layer followed by directional deposition of a dielectric and lift off of the sacrificial layer. An additional dielectric layer may now be deposited if desired.

REFERENCES:
patent: 4328263 (1982-05-01), Kurahashi et al.
patent: 4432134 (1984-02-01), Jones et al.
A. Bhattacharyya et al., "Lift-Off Insulator Process", IBM Technical Disclosure Bulletin, vol. 21, No. 9, Feb. 1979, pp. 3577-3578.
Research Disclosure-29110, "Stud Process Using Strippable Layer", Jul. 1988, p. 462.

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