Processor having a stall cache and associated method for prevent

Details Processor having a stall cache and associated method for prevent Processor having a stall cache and associated method for prevent

1993-07-07

1995-04-04

Gossage, Glenn

Boots, shoes, and leggings

364DIG1, 395375, 395650, G06F 938, G06F 1200, G06F 1300

Patent

active

054044863

ABSTRACT:
A central processing unit of a computer system which has an arithmetic logic unit, a register file, an instruction decode/fetch instruction data unit, a bus interface, a multiplexer and a stall cache. The stall cache is coupled to the instruction decode/fetch instruction data unit by a data bus and an internal instruction bus, so that the stall cache can receive and store instructions that have been delayed by an external data fetch during a load or store operation. Upon the next data access, the stall cache allows the delayed instruction to be accessed by the internal instruction bus and to then be processed by the central processing unit without the delay of an external data fetch.

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