Processor and method for preventing access to a locked memory bl

Boots – shoes – and leggings

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

395725, 364DIG1, G06F 1200, G06F 1300

Patent

active

054044820

ABSTRACT:
A processor and method for preventing access to a locked memory block in a multiprocessor computer system. The processor has a cache memory and records a memory lock in a content-addressable memory separate from the cache memory. Preferably, outstanding cache fills are recorded in the same content addressable memory as memory locks, and a memory lock or an outstanding cache fill delays the execution of a cache coherency request upon the same memory block. When a cache coherency request is received from another processor, the address of the cache coherency request is compared to addresses stored in the content addressable memory, and when there is a match, a bit in the matching entry is set to indicate a delayed request that is executed after the lock is unlocked or the cache is refilled. In a specific embodiment, a memory lock or an outstanding cache fill also stalls a processor read or write to the same memory block.

REFERENCES:
patent: 4142234 (1979-02-01), Bean et al.
patent: 4195340 (1980-03-01), Joyce
patent: 4197580 (1980-04-01), Chang et al.
patent: 4410944 (1983-10-01), Kronies
patent: 4445174 (1984-04-01), Fletcher
patent: 4502110 (1985-02-01), Saito
patent: 4527238 (1985-07-01), Ryan et al.
patent: 4561051 (1985-12-01), Rodman et al.
patent: 4587610 (1986-05-01), Rodman
patent: 4622631 (1986-11-01), Frank et al.
patent: 4654819 (1987-03-01), Stiffler et al.
patent: 4768148 (1988-08-01), Keeley et al.
patent: 4858111 (1989-08-01), Steps
patent: 4858116 (1989-08-01), Gillett, Jr. et al.
patent: 4875155 (1989-10-01), Iskitan et al.
patent: 4875160 (1989-10-01), Brown, III
patent: 4977498 (1990-12-01), Rastegar et al.
patent: 4984153 (1991-01-01), Kregness et al.
patent: 5142676 (1992-08-01), Fried et al.
patent: 5148536 (1992-09-01), Witek et al.
patent: 5155843 (1992-11-01), Stamm et al.
patent: 5276847 (1994-01-01), Kohn
Archibald et al., "Cache Coherence Protocols: Evaluation Using a Multi-Processor Simulation Model," ACM Transactions on Computer Systems, No. 4, Nov. 1986, New York, N.Y., U.S.A., pp. 273-298.
Tang, "Cache System Design in the Tightly Coupled Multiprocessor System," American Federation of Information Processing Soc., Joint Computer Conf., vol. 45: Proceedings of the National Computer Conference, New York, Jun. 7-10, 1976, U.S.A., pp. 749-753.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Processor and method for preventing access to a locked memory bl does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Processor and method for preventing access to a locked memory bl, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Processor and method for preventing access to a locked memory bl will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2385242

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.