Boundary scan architecture analog extension

Details Boundary scan architecture analog extension Boundary scan architecture analog extension

1993-02-04

1995-04-04

Cosimano, Edward R.

Excavating

364579, 364580, 371 151, 371 221, 371 225, 371 226, G06F 1520

Patent

active

054043581

ABSTRACT:
A method and apparatus provides an analog mode of operation of a standard test access bus interface based on a standard Boundary Scan architecture which is limited to use of digital signals. Circuits are included in the interface which enable this sharing of data paths at separate time intervals defined under instruction control for processing analog and digital signals thereby providing a hybrid capability without any increase in the number of lines required by the interface.

REFERENCES:
patent: 3582902 (1971-06-01), Hirtle et al.
patent: 4357703 (1982-11-01), Van Brunt
patent: 5225834 (1993-07-01), Imai et al.
patent: 5285152 (1994-02-01), Hunter
patent: 5291495 (1994-03-01), Udell, Jr.
"Mixed-Signal Testing Using Analog Scan Design" by Richard Hulse, published by Computer Design Magazine in the 1992 Analog & Mixed-Signal Design Conference Proceedings, Oct. 28-30, 1992, Section 244.

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