Synchronous type semiconductor memory device operating in synchr

Details Synchronous type semiconductor memory device operating in synchr Synchronous type semiconductor memory device operating in synchr

1994-01-31

1995-04-04

Fears, Terrell W.

Static information storage and retrieval

Addressing

Sync/clocking

365203, 365210, G11C 1300

Patent

active

054043387

ABSTRACT:
In a synchronous semiconductor memory device, memory arrays (MA) forming activation units each are divided into a plurality of small memory arrays (MK). There are provided local I/O line pairs (LIO) each for two small memory arrays. The global I/O line pairs (GIO) crossing word lines are arranged in word line shunt regions (WS). The connection switches (BS) are arranged in the crossing between the local I/O line pairs and global I/O line pairs. Each small memory array in the activated memory array is connected to the corresponding global I/O line pair through the local I/O line pair. Thereby, a plurality of bits can be simultaneously read without increasing an area occupied by interconnections. The control of connection switch is made using a sense amplifier activation signal. Global I/O lines are precharged/equalized after data are transferred to read data registers provided for data output terminal for sequential data output or into selected memory cells. External clock signal is frequency-divided to produce phase-shifted internal clock signals which are used for producing internal voltage through charge operation.

REFERENCES:
patent: 3691538 (1972-04-01), Haney et al.
patent: 4106109 (1978-08-01), Fassbender
patent: 5083296 (1992-01-01), Hara et al.
ISSCC 92 Session 9/Non-Volatile and Dynamic RAMs/Paper 9.1, 1992 IEEE International Solid-State Circuits Conference.
A 100-MHZ 4-MB Cache DRAM with Fast Copy-Back Scheme, Katsumi Dosaka et al., IEEE Journal of Solid-State Circuits, vol. 27, No. 11, Nov. 1992, pp. 1534-1539.

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