Boots – shoes – and leggings
Patent
1993-11-01
1995-04-04
Mai, Tan V.
Boots, shoes, and leggings
364748, G06F 752, G06F 738
Patent
active
054043247
ABSTRACT:
An apparatus for performing floating-point division and square root computations according to an IEEE rounding standard includes input data alignment circuitry, core iteration circuitry, remainder compare circuitry, and round and select circuitry. The core iteration circuitry includes digit selector circuitry; remainder registers; quotient logic circuitry; remainder formation circuitry; and quotient registers for storing the quotient Q, incremented quotient Q+1, and decremented quotient Q-1. The remainder formation circuitry produces sum and carry bits of the P.sub.j+1 term, which are in turn fed back to the partial remainder registers and used in subsequent iterations. The quotient logic circuitry builds the quotient Q and maintains the respective quotient Q, Q+1, Q-1 registers. The outputs of these registers are fed back to the quotient logic circuitry for use in subsequent iterations. The remainder compare circuitry comprises a remainder comparator and a logic circuit. The remainder comparator receives the sum and carry bits for the P.sub.j+1 terms and outputs the "Sign" and "Zero" bits. These bits are received by the logic circuit along with a rounding mode signal, which is indicative of the selected rounding mode, e.g., shifted or normalized round to nearest, round to zero, or round to infinity. The logic circuit outputs a round select signal that selects a quotient select signal for selecting, as the final rounded quotient, the output of one of the quotient registers Q, Q+1, or Q-1. The round and select circuitry includes a round block for positive remainders and a round block for negative remainders.
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Hewlett--Packard Company
Mai Tan V.
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