Boots – shoes – and leggings
Patent
1993-06-15
1995-04-04
Trans, Vincent N.
Boots, shoes, and leggings
364489, 364488, G06F 1560
Patent
active
054043115
ABSTRACT:
The present invention relates to a delay time optimizing method of optimizing delay times and a method of optimizing delay times in an LSI equipped with latch circuits at its input and output. The method divides a plurality of logic circuits from a combinatorial circuit located among latch circuits for outputting data related to input data in response to clocks, calculates the delay time of a path between each of the latch circuits at end points and each of the latch circuits at starting points, performing the weighting related to the delay time on each of the distinguished logic circuits located between each of the starting points and each of the end points for each path, and calculates a relative index for changing the delay time for each logic circuit.
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patent: 5197015 (1993-03-01), Hartoog et al.
patent: 5218551 (1993-06-01), Agrawal et al.
patent: 5237514 (1993-08-01), Curtin
patent: 5251147 (1993-10-01), Finnerty
"Analytical Power/Timing Optimization Technique for Digital System" by A. E. Ruehli et al., IEEE 14th DAC, 1977, pp. 142-146.
"Timing Analysis for nMOS VLSI" by N. P. Jouppi, IEEE 20th Design Automation Conference, 1983, pp. 411-418.
"Timing Influenced Layout Design" by M. Burstein et al., IEEE 22nd Design Automation Conf., 1985, pp. 124-130.
Fujitsu Limited
Trans Vincent N.
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