Single-component memory controller utilizing asynchronous state

Details Single-component memory controller utilizing asynchronous state Single-component memory controller utilizing asynchronous state

1991-05-14

1994-06-28

Shaw, Dale M.

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395275, 3642384, G06F 104

Patent

active

053255151

ABSTRACT:
An asynchronous memory controller comprises plurality of flip-flops connected in a series. The input of the first flip-flop receives a signal indicating the start of a bus cycle. The input of each succeeding flip-flop in the series is connected to the output of the preceding flip-flop. The odd-numbered flip-flops in the series are activated by a first state of a clock pulse; the even-numbered flip-flops in the series are activated by a second state of a clock pulse. Each flip-flop responds to a level of the clock pulse rather than a rising or falling edge.

REFERENCES:
patent: 4754425 (1988-06-01), Bhadriraju
patent: 4827157 (1989-05-01), Machida et al.
patent: 4870562 (1989-09-01), Kimoto et al.
patent: 4918657 (1990-04-01), Takahaski
patent: 5014188 (1991-05-01), Kawamura
Handbook For Electronics Engineering Technicians/Second Edition/Milton Kaufman/1984/pp. 15-9 to 15-10.

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