Digital sigma-delta modulator and arithmetic overflow protected

Details Digital sigma-delta modulator and arithmetic overflow protected Digital sigma-delta modulator and arithmetic overflow protected

1992-05-05

1994-06-28

Chin, Stephen

Pulse or digital communications

Repeaters

Testing

341143, H04B 1406

Patent

active

053253990

ABSTRACT:
In a digital sigma-delta modulator with multi-phase operations by time-sharing including an adder to produce multiple integration, an arrangement includes switching circuitry for alternately establishing one of: a connection between a first input of the adder and an input of the modulator; and connections between the adder output and the first input of the adder by way of a first integration delay circuit, and the adder output and a second input of the adder by way of a second delay circuit.

REFERENCES:
patent: 4202011 (1980-05-01), Koga
patent: 4528551 (1985-07-01), Agrawal et al.
patent: 5068659 (1991-11-01), Sakaguchi
Boser et al., "The Design of Sigma-Delta Modulation Analog-to-Digital Converters," IEEE Journal of Solid-State Circuits, vol. 23, No. 6, Dec. 1988, pp. 1298-1308.
Everard, "A Single-Channel PCM Codec," IEEE Transactions on Communications, vol. COM-27, No. 2, Feb. 1979, pp. 283-295.
Agrawal et al., "Design Methodology for .epsilon..DELTA.M," IEEE Communications Society International Conference on Acoustics . . . , Paris, France, May 1982, pp. 360-369.
Friedman et al., "A Dual-Channel Voice-Band PCM Codec Using .epsilon..DELTA. Modulation Technique," IEEE Journal of Solid-State Circuits, vol. 24, No. 2, Apr. 1989, pp. 274-280.
Candy, "A Use of Double Integration in Sigma Delta Modulation," IEEE Transactions on Communications, vol. Com-33, No. 3, Mar. 1985, pp. 249-258.

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