Flat semiconductor wiring layers

Details Flat semiconductor wiring layers Flat semiconductor wiring layers

1994-06-14

1995-04-04

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257752, 257758, 257773, 257775, H01L 2348

Patent

active

054040469

ABSTRACT:
The semiconductor circuit device is provided with a first wiring layer connected to a semiconductor substrate through a contact hole in an insulation film formed on a main surface of the semiconductor substrate, and a second wiring layer connected with the first wiring layer through a through-hole in an interlayer insulation film formed on the first wiring layer, wherein the first wiring is substantially flat on the contact hole and the area of the through-hole is smaller than that of the contact hole.

REFERENCES:
patent: 4403217 (1983-09-01), Becker et al.
patent: 4525709 (1985-06-01), Hareng et al.
patent: 5019531 (1991-05-01), Awaya et al.
patent: 5060045 (1991-10-01), Owada et al.
Ting et al.--J. Electrochemical Soc., vol. 136, No. 2 Feb. 1989, pp. 456-462.
J. Electrochemical Soc., vol. 136, No. 2, Feb. 1989, 99 456-462, Ting et al., "Selective Electroless Metal Deposition For Integrated Circuit Fabrication".

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