High speed parallel multiplication circuit having a reduced numb

Boots – shoes – and leggings

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

G06F 752

Patent

active

053253213

ABSTRACT:
A parallel multiplication circuit includes a plurality of Booth's decoders, a plurality of partial product generation circuits, and a plurality of full adders. Each Booth's decoder is constructed in accordance with the following decode signal generating logic:

REFERENCES:
patent: 4644488 (1987-02-01), Nathan
patent: 4813008 (1989-03-01), Shigehara et al.
patent: 4817029 (1989-03-01), Finegold
patent: 4991131 (1991-02-01), Yeh et al.
patent: 5040139 (1991-08-01), Tran
patent: 5231415 (1993-07-01), Hagihara

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

High speed parallel multiplication circuit having a reduced numb does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed parallel multiplication circuit having a reduced numb, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed parallel multiplication circuit having a reduced numb will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2381888

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.