Method of forming multilayered wiring

Details Method of forming multilayered wiring Method of forming multilayered wiring

1993-07-16

1995-04-04

Quach, T. N.

Fishing, trapping, and vermin destroying

437190, 437192, 437228, 437227, H01L 21311

Patent

active

054037816

ABSTRACT:
A multi-layered wiring structure, having a first level metal wiring layer and a second level metal wiring layer, is formed on a semiconductor substrate. A first level interlayer insulating film which has an undulation caused by the first level metal wiring layer, a second level metal wiring layer which also has an uneven surface, and a second level interlayer insulating layer are consecutively deposited on the semiconductor substrate. A reflection preventing film (TiN) of 80 nm or more thickness is deposited over the second level interlayer insulating film, and a resist layer is coated on the reflection preventing film. Then, an ultra-violet ray is irradiated through a patterning mask to make an opening corresponding to a contact hole. The reflection preventing film constrains a multi-reflection of the ultra-violet ray. Thus, an accuracy of the patterning of the contact hole is improved.

REFERENCES:
patent: 5036382 (1991-07-01), Yamaha
patent: 5190894 (1993-03-01), Taneda et al.
patent: 5219788 (1993-06-01), Abernathey et al.
Wolf et al., Silicon Processing, vol. 1, Lattice Press, 1986, pp. 407-420.

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