Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Patent
1993-04-14
1994-06-28
Larkins, William D.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
257620, 257621, 257630, H01L 2352
Patent
active
053249810
ABSTRACT:
A high power FET device includes a plated heat sink, a rear surface electrode disposed between a substrate and the heat sink, a via-hole extending through the substrate and containing a metal plating for electrically connecting the rear surface electrode and an element, such as the source electrode, of the FET device. A metallic layer extending from the rear surface to the front surface of the device protects the side walls of the substrate during handling. The side wall protection layer extends onto portions of the front surface of the substrate as a measurement electrode. The arrangement gives access to the source, drain, and gate electrodes of the device from the front surface for measuring the electrical characteristics of the device while it is still part of a wafer containing a large number of devices. Each device includes a separation groove outwardly spaced from the device and containing a metallic layer which becomes the side wall protection layer after dicing. Preferably, the separation grooves are wider and deeper than the via-holes.
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D'Asaro et al., "Plasma-Etched Via Connections to GaAs FET's", The Institute of Physics Conference Series, No. 56, Chapter 5, 1981, pp. 267-273.
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Ishikawa Takahide
Kobiki Michihiro
Yoshida Masahiro
Larkins William D.
Mitsubishi Denki & Kabushiki Kaisha
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