Boots – shoes – and leggings
Patent
1981-09-29
1984-02-14
Smith, Jerry
Boots, shoes, and leggings
G06F 1300
Patent
active
044320558
ABSTRACT:
A memory subsystem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem further includes an adder circuit, a pair of tristate operated address register circuits and timing circuits. The address circuits include a pair of tristate operated address registers which couple to the bus and to the set of address lines to each memory unit. In response to a memory request, the registers store row and column address portions of a chip address of the memory request. A multibit adder circuit which couples to the bus is connected to increment by one the low order column address portion when the least significant address bit of the memory request indicates a subboundary address condition thereby enabling access to a pair of sequential word locations. Whenever a memory request specifies an address which cannot access a double word, boundary circuits upon detecting the condition cause the timing circuits to generate only timing signals necessary for accessing the first word location.
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patent: 4000485 (1976-12-01), Barlow et al.
patent: 4181974 (1980-01-01), Lemay et al.
patent: 4185323 (1980-01-01), Johnson et al.
patent: 4236203 (1980-11-01), Curley et al.
patent: 4376972 (1983-03-01), Johnson et al.
Johnson Robert B.
Nibby, Jr. Chester M.
Salas Edward R.
Driscoll Faith F.
Honeywell Information Systems Inc.
Lee Jameson
Prasinos Nicholas
Smith Jerry
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